Lead MTS Security Engineering

ResponsibilitiesImplement (RTL-level in Verilog) hardware IP blocks that are part of Rambus Security’s IP portfolio (Root of Trust, cryptographic cores, etc.) Develop side-channel analysis (SCA) and fault injection attack (FIA) countermeasures for symmetric- and public-key (including post-quantum) cryptography hardware cores Assist DPA and Fault evaluation Research, invent and patent/publish new techniques in the field of SCA countermeasures, fault resistance and efficient hardware designs Represent Rambus Security at international workshops and conferences Create internal and external documentation Assist verification engineers with test plan creation and debugging Assist with EDA tool-related tasks, such as synthesis, static-timing analysis, logical equivalency checking, linting, continuous integration, and help improve flows and scripts QualificationsExperience and Skills MS/PhD degree in electrical or computer engineering required 6 plus years working in secure hardware design, a PhD degree may substitute the work experience requirement Demonstrated proficiency in Verilog and digital design. Familiarity with front-end ASIC design flows, including design, simulation, synthesis, timing analysis, logical equivalence checking, and linting/rule checking. Experience with back-end flows, especially place-and-route, is beneficial. Expertise in some or all of the following areas is beneficial: Knowledge of HW security architectures and IPs (secure MCU cores, cryptographic co-processors, secure memories, secure elements, smart cards) Design and implementation of efficient cryptographic algorithms Experience on side-channel and fault attacks and countermeasures High performance CPU architecture and design. Clock and reset domain crossing techniques. Hardware development experience in UNIX/Linux environments, including supporting tasks such as shell scripting and basic Perl scripts. Ability to work with technical writers in the production of technical documentation. Tools/Technologies Verilog, SystemVerilog, Perl Shell scripting, Python, Tcl Unix, Linux Xilinx Vivado Front-end ASIC design tools and simulation Personal Attributes Able and willing to work in an international, team-oriented, collaborative environment A demonstrated ability to prioritize and execute tasks so as to achieve goals in an innovative and fast paced environment Proven analytical and creative problem-solving abilities. Passionate about writing clean and neat code that adheres to coding guidelines. About Rambus With 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.